`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:38:10 11/20/2013
// Design Name:   cavlc_2_4_lut
// Module Name:   G:/Xilinx_Proj/H_264_test/nc_2_4_lut_test.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: cavlc_2_4_lut
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module nc_2_4_lut_test;

	// Inputs
	reg [15:0] data;

	// Outputs
	wire [2:0] Tls;
	wire [4:0] TotalCoeff;
	wire [1:0] Bits;

	reg clk,rst;
	reg [8:0]cnt;
	// Instantiate the Unit Under Test (UUT)
	cavlc_nc_2_4_lut uut (
		.data(data), 
		.Tls(Tls), 
		.TotalCoeff(TotalCoeff), 
		.Bits(Bits)
	);

	initial begin
		// Initialize Inputs
		data = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#100 rst=1; 
		 #100 rst=0; 
		 #100 rst=1; 
		 clk=0;
		 cnt=0;
	end
      
always begin #20 clk=~clk; end
  
always @(negedge rst or posedge clk) begin
		if(!rst) begin
			cnt<=0;
		end
		else begin
			case(cnt)
			0:begin
				data<=16'b0000000000000011;cnt<=cnt+1'b1;
			end
			1:begin
				data<=16'b0000000000110100;cnt<=cnt+1'b1;
			end
			2:begin
				data<=16'b0000000000000001;cnt<=cnt+1'b1;
			end
			3:begin
				data<=16'b0000000000111000;cnt<=cnt+1'b1;
			end
			4:begin
				data<=16'b0000000000011100;cnt<=cnt+1'b1;
			end
			5:begin
				data<=16'b0000000000000110;cnt<=cnt+1'b1;
			end
			6:begin
				data<=16'b0000000001110000;cnt<=cnt+1'b1;
			end
			7:begin
				data<=16'b0000000000010100;cnt<=cnt+1'b1;
			end
			8:begin
				data<=16'b0000000000100100;cnt<=cnt+1'b1;
			end
			9:begin
				data<=16'b0000000000001010;cnt<=cnt+1'b1;
			end
			10:begin
				data<=16'b0000000011100000;cnt<=cnt+1'b1;
			end
			11:begin
				data<=16'b000000000011000;cnt<=cnt+1'b1;
			end
			12:begin
				data<=16'b000000000101000;cnt<=cnt+1'b1;
			end
			13:begin
				data<=16'b0000000000000010;cnt<=cnt+1'b1;
			end
			14:begin
				data<=16'b0000000000100000;cnt<=cnt+1'b1;
			end
			15:begin
				data<=16'b0000000000110000;cnt<=cnt+1'b1;
			end
			16:begin
				data<=16'b0000000001010000;cnt<=cnt+1'b1;
			end
			17:begin
				data<=16'b0000000000001100;cnt<=cnt+1'b1;
			end
			18:begin
				data<=16'b0000000111000000;cnt<=cnt+1'b1;;
			end
			19:begin
				data<=16'b0000000001100000;cnt<=cnt+1'b1;
			end
			20:begin
				data<=16'b0000000010100000;cnt<=cnt+1'b1;
			end
			21:begin
				data<=16'b0000000000000100;cnt<=cnt+1'b1;
			end
			22:begin
				data<=16'b0000011110000000;cnt<=cnt+1'b1;
			end
			23:begin
				data<=16'b0000000011000000;cnt<=cnt+1'b1;
			end
			24:begin
				data<=16'b0000000101000000;cnt<=cnt+1'b1;
			end
			25:begin
				data<=16'b0000000000001000;cnt<=cnt+1'b1;
			end
			26:begin
				data<=16'b0000011010000000;cnt<=cnt+1'b1;
			end
			27:begin
				data<=16'b0000001110000000;cnt<=cnt+1'b1;
			end
			28:begin
				data<=16'b0000010110000000;cnt<=cnt+1'b1;
			end
			29:begin
				data<=16'b0000000000010000;cnt<=cnt+1'b1;
			end
			30:begin
				data<=16'b0000111100000000;cnt<=cnt+1'b1;
			end
			31:begin
				data<=16'b0000001010000000;cnt<=cnt+1'b1;
			end
			32:begin
				data<=16'b0000010010000000;cnt<=cnt+1'b1;
			end
			33:begin
				data<=16'b0000000001000000;cnt<=cnt+1'b1;
			end
			34:begin
				data<=16'b0000110100000000;cnt<=cnt+1'b1;
			end
			35:begin
				data<=16'b0000011100000000;cnt<=cnt+1'b1;
			end
			36:begin
				data<=16'b0000101100000000;cnt<=cnt+1'b1;
			end
			37:begin
				data<=16'b0000000110000000;cnt<=cnt+1'b1;
			end
			38:begin
				data<=16'b0000000100000000;cnt<=cnt+1'b1;
			end
			39:begin
				data<=16'b0000010100000000;cnt<=cnt+1'b1;
			end
			40:begin
				data<=16'b0000100100000000;cnt<=cnt+1'b1;
			end
			41:begin
				data<=16'b0000000010000000;cnt<=cnt+1'b1;
			end
			42:begin
				data<=16'b0001111000000000;cnt<=cnt+1'b1;
			end
			43:begin
				data<=16'b0000111000000000;cnt<=cnt+1'b1;
			end
			44:begin
				data<=16'b0001011000000000;cnt<=cnt+1'b1;
			end
			45:begin
				data<=16'b0000001100000000;cnt<=cnt+1'b1;
			end
			46:begin
				data<=16'b0001101000000000;cnt<=cnt+1'b1;
			end
			47:begin
				data<=16'b0000101000000000;cnt<=cnt+1'b1;
			end
			48:begin
				data<=16'b0001001000000000;cnt<=cnt+1'b1;
			end
			49:begin
				data<=16'b0000011000000000;cnt<=cnt+1'b1;
			end
			50:begin
				data<=16'b0001110000000000;cnt<=cnt+1'b1;
			end
			51:begin
				data<=16'b0011010000000000;cnt<=cnt+1'b1;
			end
			52:begin
				data<=16'b0000110000000000;cnt<=cnt+1'b1;
			end
			53:begin
				data<=16'b0000001000000000;cnt<=cnt+1'b1;
			end
			54:begin
				data<=16'b0010010000000000;cnt<=cnt+1'b1;
			end
			55:begin
				data<=16'b0000010000000000;cnt<=cnt+1'b1;
			end
			56:begin
				data<=16'b0001010000000000;cnt<=cnt+1'b1;
			end
			57:begin
				data<=16'b0001000000000000;cnt<=cnt+1'b1;
			end
			58:begin
				data<=16'b0011100000000000;cnt<=cnt+1'b1;
			end
			59:begin
				data<=16'b0001100000000000;cnt<=cnt+1'b1;
			end
			60:begin
				data<=16'b0010100000000000;cnt<=cnt+1'b1;
			end
			61:begin
				data<=16'b0000100000000000;cnt<=7'd61;
			end
			endcase
		end
end			

		
endmodule

